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1. 
Model-Driven Design Using IEC 61499 A Synchronous Approach for Embedded and Automation Systems için kapak resmi
Model-Driven Design Using IEC 61499 A Synchronous Approach for Embedded and Automation Systems
Model-Driven Design Using IEC 61499 A Synchronous Approach for Embedded and Automation Systems
Yazar 
Yoong, Li Hsien. author.
http://dx.doi.org/10.1007/978-3-319-10521-5
Format: 
Electronic Resources
Alıntı: 
main vehicle for defining an unambiguous semantics that ensures determinism and deadlock freedom. The
2. 
Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design için kapak resmi
Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design
Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design
Yazar 
Chen, Weiwei. author.
http://dx.doi.org/10.1007/978-3-319-08753-5
Format: 
Electronic Resources
Alıntı: 
simulation execution semantics for ESL models; • Discusses discrete event simulation, along with synchronous
3. 
Digital VLSI Design with Verilog A Textbook from Silicon Valley Polytechnic Institute için kapak resmi
Digital VLSI Design with Verilog A Textbook from Silicon Valley Polytechnic Institute
Digital VLSI Design with Verilog A Textbook from Silicon Valley Polytechnic Institute
Yazar 
Williams, John Michael. author.
http://dx.doi.org/10.1007/978-3-319-04789-8
Format: 
Electronic Resources
Alıntı: 
language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are
4. 
SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications için kapak resmi
SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
Yazar 
Mehta, Ashok B. author.
http://dx.doi.org/10.1007/978-3-319-30539-4
Format: 
Electronic Resources
Alıntı: 
entirety the latest IEEE-1800 2012 LRM syntax and semantics; · Covers both SystemVerilog Assertions and
5. 
SVA: The Power of Assertions in SystemVerilog için kapak resmi
SVA: The Power of Assertions in SystemVerilog
SVA: The Power of Assertions in SystemVerilog
Yazar 
Cerny, Eduard. author.
http://dx.doi.org/10.1007/978-3-319-07139-8
Format: 
Electronic Resources
Alıntı: 
Verification and Models.- Formal Semantics.- Part VI. Advanced Checkers -- Checkers in Formal Verification
6. 
A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof için kapak resmi
A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof
A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof
Yazar 
Kovalev, Mikhail. author.
http://dx.doi.org/10.1007/978-3-319-13906-7
Format: 
Electronic Resources
Alıntı: 
Sequences -- Sequential Memory Semantics -- Sequentially Consistent Memory Systems -- Memory System Hardware
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