Preface -- About the Author -- Part I: Original Contributions -- Devices and Circuits for Phase-Locked Systems -- Delay-Locked Loops - An Overview -- Delta-Sigma Fractional-N Phase-Locked Loops -- Design Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems -- Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers -- Part II: Devices -- Physics-Based Closed-Form Inductance Expression for Compact Modeling of Integrated Spiral Inductors -- The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's -- Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC's -- Stacked Inductors and Transformers in CMOS Technology -- Estimation Methods for Quality Factors of Inductors Fabricated in Silicon Integrated Circuit Process Technologies -- A Q-Factor Enhancement Technique for MMIC Inductors -- On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's -- The Effects of a Ground Shield on the Characteristics and Performance of Spiral Inductors -- Temperature Dependence of Q and Inductance in Spiral Inductors Fabricated in a Silicon-Germanium/BiCMOS Technology -- Substrate Noise Coupling Through Planar Spiral Inductor -- Design of High-Q Varactors for Low-Power Wireless Applications Using a Standard CMOS Process -- On the Use of MOS Varactors in RF VCO's -- Part III: Phase Noise and Jitter -- Low-Noise Voltage-Controlled Oscillators Using Enhanced LC-Tanks -- A Study of Phase Noise in CMOS Oscillators -- A General Theory of Phase Noise in Electrical Oscillators -- Physical Processes of Phase Noise in Differential LC Oscillators -- Phase Noise in LC Oscillators -- The Effect of Varactor Nonlinearity on the Phase Noise of Completely Integrated VCOs -- Jitter in Ring Oscillators -- Jitter and Phase Noise in Ring Oscillators -- A Study of Oscillator Jitter Due to Supply and Substrate Noise -- Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise.

On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops -- Part IV: Building Blocks -- A Low-Noise, Low-Power VCO with Automatic Amplitude Control for Wireless Applications -- A Fully Integrated VCO at 2 GHz -- Tail Current Noise Suppression in RF CMOS VCOs -- Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS -- Analysis and Design of an Optimally Coupled 5-GHz Quadrature LC Oscillator -- A 1.57-GHz Fully Integrated Very Low-Phase-Noise Quadrature VCO -- A Low-Phase-Noise 5GHz Quadrature CMOS VCO Using Common-Mode Inductive Coupling -- An Integrated 10/5GHz Injection-Locked Quadrature LC VCO in a 0.18[mu]m Digital CMOS Process -- Rotary Traveling-Wave Oscillator Arrays: A New Clock Technology -- 35-GHz Static and 48-GHz Dynamic Frequency Divider IC's Using 0.2-[mu]m AlGaAs/GaAs-HEMT's -- Superharmonic Injection-Locked Frequency Dividers -- A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-[mu]m CMOS Technology -- A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-[mu]m CMOS -- A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops -- High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler -- A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC) -- A Simple Precharged CMOS Phase Frequency Detector -- Part V: Clock Generation by PLLs and DLLs -- A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation -- A Low Jitter 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3 V/5 V Operation -- Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques -- A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz -- A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL -- Active GHz Clock Network Using Distributed PLLs -- A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control -- A Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless 0.18-[mu]m CMOS PLL Based on a Sample-Reset Loop Filter.

A Dual-Loop Delay-Locked Loop Using Multiple Voltage-Controlled Delay Lines -- An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance -- A Semidigital Dual Delay-Locked Loop -- A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle -- A Portable Digital DLL for High-Speed CMOS Interface Circuits -- CMOS DLL-Base 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator -- A 1.5V 86 mW/ch 8-Channel 622-3125-Mb/s/ch CMOS SerDes Macrocell with Selectable Mux/Demux Ratio -- A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM -- A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM -- Part VI: RF Synthesis -- An Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time -- A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers -- A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver -- A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-[mu]m CMOS Technology -- Fast Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector -- Low-Power Dividerless Frequency Synthesis Using Aperture Phase Detection -- A Stabilization Technique for Phase-Locked Frequency Synthesizers -- A Modeling Approach for [Sigma]-[Delta] Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis -- A Fully Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems -- A 1.1-GHz CMOS Fraction-N Frequency Synthesizer With a 3-b Third-Order [Sigma]-[Delta] Modulator -- A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching -- A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation -- A CMOS Monolothic [Sigma][Delta]-Controlled Fractional-N Frequency Synthesizer for DSC-1800.

Part VII: Clock and Data Recovery -- A 2.5-Gb/s Clock and Data Recovery IC with Tunable Jitter Characteristics for Use in LAN's and WAN's -- Clock/Data Recovery PLL Using Half-Frequency Clock -- A 0.5-[mu]m CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling -- A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability -- SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application -- A Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate -- A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector -- A 10-Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection -- A 10-Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18[mu]m CMOS -- A 40-Gb/s Integrated Clock and Data Recovery Circuit in a 50-GHz f[subscript T] Silicon Bipolar Technology -- A Fully Integrated 40-Gb/s Clock and Data Recovery IC With 1:4 DEMUX in SiGe Technology -- Clock and Data Recovery IC for 40-Gb/s Fiber-Optic Receiver -- Index.