Five Nodes Are Sufficient for Hybrid Networks of Evolutionary Processors to Be Computationally Complete -- Learning Two-Input Linear and Nonlinear Analog Functions with a Simple Chemical System -- Scaled Tree Fractals Do not Strictly Self-assemble -- GUBS a Language for Synthetic Biology: Specification and Compilation -- Modeling Syntactic Complexity with P Systems: A Preview -- Simulating Cancer Growth Using Cellular Automata to Detect Combination Drug Targets -- Towards an MP Model for B Lymphocytes Maturation -- Pseudo-inversion on Formal Languages -- Reverse-Engineering Nonlinear Analog Circuits with Evolutionary Computation -- Steps toward Developing an Artificial Cell Signaling Model Applied to Distributed Fault Detection -- Dynamic Adaptive Neural Network Array -- Unconventional Arithmetic: A System for Computation Using Action Potentials -- Reservoir Computing Approach to Robust Computation Using Unreliable Nanoscale Networks -- On DNA-Based Gellular Automata -- Doubles and Negatives are Positive (in Self-assembly) -- On String Languages Generated by Sequential Spiking Neural P Systems Based on Maximum Spike Number -- Languages Associated with Crystallographic Symmetry -- An Energy-Efficient Computing Approach by Filling the Connectome Gap -- Fast Arithmetic in Algorithmic Self-assembly -- Pattern Formation by Spatially Organized Approximate Majority Reactions -- Mecobo: A Hardware and Software Platform for in Materio Evolution -- Compact Realization of Reversible Turing Machines by 2-State Reversible Logic Elements -- Universal Computation in the Prisoner’s Dilemma Game -- Exact Simulation of One-Dimensional Chaotic Dynamical Systems Using Algebraic Numbers -- Artificial Astrocyte Networks, as Components in Artificial Neural Networks -- Quantum, Stochastic, and Pseudo Stochastic Languages with Few States -- Phase Transition and Strong Predictability -- PHLOGON: PHase-Based LOGic Using Oscillatory Nano-Systems -- Size-Separable Tile Self-assembly: A Tight Bound for Temperature-1 Mismatch-Free Systems -- Development of Physical Super-Turing Analog Hardware.