Search Results for Field programmable gate arrays.SirsiDynix Enterprisehttps://catalog.tedu.edu.tr/client/tr_TR/defaulttr/defaulttr/qu$003dField$002bprogrammable$002bgate$002barrays.$0026ps$003d300?2025-07-06T15:18:05ZDigital Signal Processing with Field Programmable Gate Arraysent://SD_ILS/0/SD_ILS:239042025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Meyer-Baese, Uwe. author.<br/><a href="http://dx.doi.org/10.1007/978-3-642-45309-0">http://dx.doi.org/10.1007/978-3-642-45309-0</a><br/>Format: Electronic Resources<br/>Multiple Constant Multiplication Optimizations for Field Programmable Gate Arraysent://SD_ILS/0/SD_ILS:184942025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Kumm, Martin. author.<br/><a href="http://dx.doi.org/10.1007/978-3-658-13323-8">http://dx.doi.org/10.1007/978-3-658-13323-8</a><br/>Format: Electronic Resources<br/>Design for embedded image processing on FPGAsent://SD_ILS/0/SD_ILS:154862025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Bailey, Donald G. (Donald Graeme), 1962-<br/>Abstract with links to resource <a href="http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6016259">http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6016259</a><br/>Format: Electronic Resources<br/>Advanced FPGA design : architecture, implementation, and optimizationent://SD_ILS/0/SD_ILS:149782025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Kilts, Steve, 1978- author.<br/>Abstract with links to resource <a href="http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5201491">http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5201491</a><br/>Format: Electronic Resources<br/>Functionality-Enhanced Devices An alternative to Moore's Lawent://SD_ILS/0/SD_ILS:2208782025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Gaillardon, Pierre-Emmanuel, ed.<br/><a href="http://dx.doi.org/10.1049/PBCS039E">http://dx.doi.org/10.1049/PBCS039E</a><br/>Format: Electronic Resources<br/>Authentication Technologies for Cloud Computing, IoT and Big Dataent://SD_ILS/0/SD_ILS:2210192025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Alginahi, Yasser M., ed.<br/><a href="http://dx.doi.org/10.1049/PBSE009E">http://dx.doi.org/10.1049/PBSE009E</a><br/>Format: Electronic Resources<br/>Logic Synthesis for FPGA-Based Finite State Machinesent://SD_ILS/0/SD_ILS:169042025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Barkalov, Alexander. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-24202-6">http://dx.doi.org/10.1007/978-3-319-24202-6</a><br/>Format: Electronic Resources<br/>Synthesis and Optimization of FPGA-Based Systemsent://SD_ILS/0/SD_ILS:205272025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Sklyarov, Valery. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-04708-9">http://dx.doi.org/10.1007/978-3-319-04708-9</a><br/>Format: Electronic Resources<br/>Logic Synthesis for Finite State Machines Based on Linear Chains of States Foundations, Recent Developments and Challengesent://SD_ILS/0/SD_ILS:2224302025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Barkalov, Alexander. author.<br/><a href="https://doi.org/10.1007/978-3-319-59837-6">https://doi.org/10.1007/978-3-319-59837-6</a><br/>Format: Electronic Resources<br/>Separation Logic for High-level Synthesisent://SD_ILS/0/SD_ILS:2253752025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Winterstein, Felix. author.<br/><a href="https://doi.org/10.1007/978-3-319-53222-6">https://doi.org/10.1007/978-3-319-53222-6</a><br/>Format: Electronic Resources<br/>Engineering Applications of FPGAs Chaotic Systems, Artificial Neural Networks, Random Number Generators, and Secure Communication Systemsent://SD_ILS/0/SD_ILS:179202025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Tlelo-Cuautle, Esteban. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-34115-6">http://dx.doi.org/10.1007/978-3-319-34115-6</a><br/>Format: Electronic Resources<br/>FPGA Based Accelerators for Financial Applicationsent://SD_ILS/0/SD_ILS:223752025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar De Schryver, Christian. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-319-15407-7">http://dx.doi.org/10.1007/978-3-319-15407-7</a><br/>Format: Electronic Resources<br/>High Performance Integer Arithmetic Circuit Design on FPGA Architecture, Implementation and Design Automationent://SD_ILS/0/SD_ILS:187572025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Palchaudhuri, Ayan. author.<br/><a href="http://dx.doi.org/10.1007/978-81-322-2520-1">http://dx.doi.org/10.1007/978-81-322-2520-1</a><br/>Format: Electronic Resources<br/>Fuzzy Logic Type 1 and Type 2 Based on LabVIEW™ FPGAent://SD_ILS/0/SD_ILS:170812025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Ponce-Cruz, Pedro. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-26656-5">http://dx.doi.org/10.1007/978-3-319-26656-5</a><br/>Format: Electronic Resources<br/>Three-Dimensional Design Methodologies for Tree-based FPGA Architectureent://SD_ILS/0/SD_ILS:229052025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Pangracious, Vinod. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-19174-4">http://dx.doi.org/10.1007/978-3-319-19174-4</a><br/>Format: Electronic Resources<br/>A Route to Chaos Using FPGAs Volume I: Experimental Observationsent://SD_ILS/0/SD_ILS:227782025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Muthuswamy, Bharathwaj. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-18105-9">http://dx.doi.org/10.1007/978-3-319-18105-9</a><br/>Format: Electronic Resources<br/>Real-time systems design and analysisent://SD_ILS/0/SD_ILS:150662025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Laplante, Phil, author.<br/>Abstract with links to resource <a href="http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5237056">http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5237056</a><br/>Format: Electronic Resources<br/>High-Speed Decoders for Polar Codesent://SD_ILS/0/SD_ILS:2257182025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Giard, Pascal. author.<br/><a href="https://doi.org/10.1007/978-3-319-59782-9">https://doi.org/10.1007/978-3-319-59782-9</a><br/>Format: Electronic Resources<br/>Applied Reconfigurable Computing 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedingsent://SD_ILS/0/SD_ILS:225172025-07-06T15:18:05Z2025-07-06T15:18:05ZYazar Sano, Kentaro. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-319-16214-0">http://dx.doi.org/10.1007/978-3-319-16214-0</a><br/>Format: Electronic Resources<br/>