Search Results for Engineering. - Narrowed by: Circuits and Systems. - Logic design.SirsiDynix Enterprisehttps://catalog.tedu.edu.tr/client/tr_TR/defaulttr/defaulttr/qu$003dEngineering.$0026qf$003dSUBJECT$002509Konu$002509Circuits$002band$002bSystems.$002509Circuits$002band$002bSystems.$0026qf$003dSUBJECT$002509Konu$002509Logic$002bdesign.$002509Logic$002bdesign.$0026ic$003dtrue$0026ps$003d300?2024-07-14T19:36:28ZDigital Logic Design Using Verilog Coding and RTL Synthesisent://SD_ILS/0/SD_ILS:187922024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Taraate, Vaibbhav. author.<br/><a href="http://dx.doi.org/10.1007/978-81-322-2791-5">http://dx.doi.org/10.1007/978-81-322-2791-5</a><br/>Format: Electronic Resources<br/>Advanced Symbolic Analysis for VLSI Systems Methods and Applicationsent://SD_ILS/0/SD_ILS:199062024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Shi, Guoyong. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4939-1103-5">http://dx.doi.org/10.1007/978-1-4939-1103-5</a><br/>Format: Electronic Resources<br/>High Performance Integer Arithmetic Circuit Design on FPGA Architecture, Implementation and Design Automationent://SD_ILS/0/SD_ILS:187572024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Palchaudhuri, Ayan. author.<br/><a href="http://dx.doi.org/10.1007/978-81-322-2520-1">http://dx.doi.org/10.1007/978-81-322-2520-1</a><br/>Format: Electronic Resources<br/>Fundamentals of Electronic Systems Designent://SD_ILS/0/SD_ILS:2241092024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Lienig, Jens. author.<br/><a href="https://doi.org/10.1007/978-3-319-55840-0">https://doi.org/10.1007/978-3-319-55840-0</a><br/>Format: Electronic Resources<br/>New Data Structures and Algorithms for Logic Synthesis and Verificationent://SD_ILS/0/SD_ILS:2239642024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Amaru, Luca Gaetano. author.<br/><a href="https://doi.org/10.1007/978-3-319-43174-1">https://doi.org/10.1007/978-3-319-43174-1</a><br/>Format: Electronic Resources<br/>Reliable and Energy Efficient Streaming Multiprocessor Systemsent://SD_ILS/0/SD_ILS:2245582024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Das, Anup Kumar. author.<br/><a href="https://doi.org/10.1007/978-3-319-69374-3">https://doi.org/10.1007/978-3-319-69374-3</a><br/>Format: Electronic Resources<br/>Introduzione al Progetto di Sistemi Digitalient://SD_ILS/0/SD_ILS:2240142024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Donzellini, Giuliano. author.<br/><a href="https://doi.org/10.1007/978-88-470-3963-6">https://doi.org/10.1007/978-88-470-3963-6</a><br/>Format: Electronic Resources<br/>Simulation and Optimization of Digital Circuits Considering and Mitigating Destabilizing Factorsent://SD_ILS/0/SD_ILS:2212192024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Melikyan, Vazgen. author.<br/><a href="https://doi.org/10.1007/978-3-319-71637-4">https://doi.org/10.1007/978-3-319-71637-4</a><br/>Format: Electronic Resources<br/>Introduction to Logic Circuits & Logic Design with Verilogent://SD_ILS/0/SD_ILS:2253862024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar LaMeres, Brock J. author.<br/><a href="https://doi.org/10.1007/978-3-319-53883-9">https://doi.org/10.1007/978-3-319-53883-9</a><br/>Format: Electronic Resources<br/>Testing of Interposer-Based 2.5D Integrated Circuitsent://SD_ILS/0/SD_ILS:2238932024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Wang, Ran. author.<br/><a href="https://doi.org/10.1007/978-3-319-54714-5">https://doi.org/10.1007/978-3-319-54714-5</a><br/>Format: Electronic Resources<br/>Separation Logic for High-level Synthesisent://SD_ILS/0/SD_ILS:2253752024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Winterstein, Felix. author.<br/><a href="https://doi.org/10.1007/978-3-319-53222-6">https://doi.org/10.1007/978-3-319-53222-6</a><br/>Format: Electronic Resources<br/>Design of FPGA-Based Computing Systems with OpenCLent://SD_ILS/0/SD_ILS:2254812024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Waidyasooriya, Hasitha Muthumala. author.<br/><a href="https://doi.org/10.1007/978-3-319-68161-0">https://doi.org/10.1007/978-3-319-68161-0</a><br/>Format: Electronic Resources<br/>Introduction to Logic Circuits & Logic Design with VHDLent://SD_ILS/0/SD_ILS:2241852024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar LaMeres, Brock J. author.<br/><a href="https://doi.org/10.1007/978-3-319-34195-8">https://doi.org/10.1007/978-3-319-34195-8</a><br/>Format: Electronic Resources<br/>ASIC/SoC Functional Design Verification A Comprehensive Guide to Technologies and Methodologiesent://SD_ILS/0/SD_ILS:2243732024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Mehta, Ashok B. . author.<br/><a href="https://doi.org/10.1007/978-3-319-59418-7">https://doi.org/10.1007/978-3-319-59418-7</a><br/>Format: Electronic Resources<br/>From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Acceleratorsent://SD_ILS/0/SD_ILS:2250912024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Rahimi, Abbas. author.<br/><a href="https://doi.org/10.1007/978-3-319-53768-9">https://doi.org/10.1007/978-3-319-53768-9</a><br/>Format: Electronic Resources<br/>Principles and Structures of FPGAsent://SD_ILS/0/SD_ILS:2218482024-07-14T19:36:28Z2024-07-14T19:36:28ZYazar Amano, Hideharu. editor.<br/><a href="https://doi.org/10.1007/978-981-13-0824-6">https://doi.org/10.1007/978-981-13-0824-6</a><br/>Format: Electronic Resources<br/>