Search Results for - Narrowed by: Electronics. - Processor Architectures.SirsiDynix Enterprisehttps://catalog.tedu.edu.tr/client/tr_TR/defaulttr/defaulttr/qf$003dSUBJECT$002509Konu$002509Electronics.$002509Electronics.$0026qf$003dSUBJECT$002509Konu$002509Processor$002bArchitectures.$002509Processor$002bArchitectures.$0026ps$003d300$0026isd$003dtrue?2024-06-20T02:11:01ZLanguages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2016ent://SD_ILS/0/SD_ILS:2234092024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Fummi, Franco. editor.<br/><a href="https://doi.org/10.1007/978-3-319-62920-9">https://doi.org/10.1007/978-3-319-62920-9</a><br/>Format: Electronic Resources<br/>Fundamentals of Electromigration-Aware Integrated Circuit Designent://SD_ILS/0/SD_ILS:2255192024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Lienig, Jens. author.<br/><a href="https://doi.org/10.1007/978-3-319-73558-0">https://doi.org/10.1007/978-3-319-73558-0</a><br/>Format: Electronic Resources<br/>Machine Learning for Model Order Reductionent://SD_ILS/0/SD_ILS:2255282024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Mohamed, Khaled Salah. author.<br/><a href="https://doi.org/10.1007/978-3-319-75714-8">https://doi.org/10.1007/978-3-319-75714-8</a><br/>Format: Electronic Resources<br/>Symbolic Parallelization of Nested Loop Programsent://SD_ILS/0/SD_ILS:2258082024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Tanase, Alexandru-Petru. author.<br/><a href="https://doi.org/10.1007/978-3-319-73909-0">https://doi.org/10.1007/978-3-319-73909-0</a><br/>Format: Electronic Resources<br/>Formal System Verification State-of the-Art and Future Trendsent://SD_ILS/0/SD_ILS:2261072024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Drechsler, Rolf. editor.<br/><a href="https://doi.org/10.1007/978-3-319-57685-5">https://doi.org/10.1007/978-3-319-57685-5</a><br/>Format: Electronic Resources<br/>Dependable Multicore Architectures at Nanoscaleent://SD_ILS/0/SD_ILS:2259892024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Ottavi, Marco. editor.<br/><a href="https://doi.org/10.1007/978-3-319-54422-9">https://doi.org/10.1007/978-3-319-54422-9</a><br/>Format: Electronic Resources<br/>Embedded System Design Embedded Systems Foundations of Cyber-Physical Systems, and the Internet of Thingsent://SD_ILS/0/SD_ILS:2259432024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Marwedel, Peter. author.<br/><a href="https://doi.org/10.1007/978-3-319-56045-8">https://doi.org/10.1007/978-3-319-56045-8</a><br/>Format: Electronic Resources<br/>Energy Efficient Embedded Video Processing Systems A Hardware-Software Collaborative Approachent://SD_ILS/0/SD_ILS:2266132024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Khan, Muhammad Usman Karim. author.<br/><a href="https://doi.org/10.1007/978-3-319-61455-7">https://doi.org/10.1007/978-3-319-61455-7</a><br/>Format: Electronic Resources<br/>Advanced Techniques for Power, Energy, and Thermal Management for Clustered Manycoresent://SD_ILS/0/SD_ILS:2234292024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Pagani, Santiago. author.<br/><a href="https://doi.org/10.1007/978-3-319-77479-4">https://doi.org/10.1007/978-3-319-77479-4</a><br/>Format: Electronic Resources<br/>Timing Performance of Nanometer Digital Circuits Under Process Variationsent://SD_ILS/0/SD_ILS:2230402024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Champac, Victor. author.<br/><a href="https://doi.org/10.1007/978-3-319-75465-9">https://doi.org/10.1007/978-3-319-75465-9</a><br/>Format: Electronic Resources<br/>Digital Storage in Consumer Electronics The Essential Guideent://SD_ILS/0/SD_ILS:2239262024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Coughlin, Thomas M. author.<br/><a href="https://doi.org/10.1007/978-3-319-69907-3">https://doi.org/10.1007/978-3-319-69907-3</a><br/>Format: Electronic Resources<br/>Contactless VLSI Measurement and Testing Techniquesent://SD_ILS/0/SD_ILS:2238952024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Sayil, Selahattin. author.<br/><a href="https://doi.org/10.1007/978-3-319-69673-7">https://doi.org/10.1007/978-3-319-69673-7</a><br/>Format: Electronic Resources<br/>Automated Validation & Verification of UML/OCL Models Using Satisfiability Solversent://SD_ILS/0/SD_ILS:2241912024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Przigoda, Nils. author.<br/><a href="https://doi.org/10.1007/978-3-319-72814-8">https://doi.org/10.1007/978-3-319-72814-8</a><br/>Format: Electronic Resources<br/>Parallel Sparse Direct Solver for Integrated Circuit Simulationent://SD_ILS/0/SD_ILS:2251782024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Chen, Xiaoming. author.<br/><a href="https://doi.org/10.1007/978-3-319-53429-9">https://doi.org/10.1007/978-3-319-53429-9</a><br/>Format: Electronic Resources<br/>Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniquesent://SD_ILS/0/SD_ILS:2229292024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Martins, Ricardo. author.<br/><a href="https://doi.org/10.1007/978-3-319-34060-9">https://doi.org/10.1007/978-3-319-34060-9</a><br/>Format: Electronic Resources<br/>Designing with Xilinx® FPGAs Using Vivadoent://SD_ILS/0/SD_ILS:2251622024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Churiwala, Sanjay. editor.<br/><a href="https://doi.org/10.1007/978-3-319-42438-5">https://doi.org/10.1007/978-3-319-42438-5</a><br/>Format: Electronic Resources<br/>Foundations of Hardware IP Protectionent://SD_ILS/0/SD_ILS:2263762024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Bossuet, Lilian. editor.<br/><a href="https://doi.org/10.1007/978-3-319-50380-6">https://doi.org/10.1007/978-3-319-50380-6</a><br/>Format: Electronic Resources<br/>Embedded Systems Design with Special Arithmetic and Number Systemsent://SD_ILS/0/SD_ILS:2212912024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Molahosseini, Amir Sabbagh. editor.<br/><a href="https://doi.org/10.1007/978-3-319-49742-6">https://doi.org/10.1007/978-3-319-49742-6</a><br/>Format: Electronic Resources<br/>Hardware IP Security and Trustent://SD_ILS/0/SD_ILS:2221512024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Mishra, Prabhat. editor.<br/><a href="https://doi.org/10.1007/978-3-319-49025-0">https://doi.org/10.1007/978-3-319-49025-0</a><br/>Format: Electronic Resources<br/>Digital Systems From Logic Gates to Processorsent://SD_ILS/0/SD_ILS:2226452024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Deschamps, Jean-Pierre. author.<br/><a href="https://doi.org/10.1007/978-3-319-41198-9">https://doi.org/10.1007/978-3-319-41198-9</a><br/>Format: Electronic Resources<br/>Hardware Protection through Obfuscationent://SD_ILS/0/SD_ILS:2236982024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Forte, Domenic. editor.<br/><a href="https://doi.org/10.1007/978-3-319-49019-9">https://doi.org/10.1007/978-3-319-49019-9</a><br/>Format: Electronic Resources<br/>Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effectsent://SD_ILS/0/SD_ILS:2216532024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Lourenço, Nuno. author.<br/><a href="https://doi.org/10.1007/978-3-319-42037-0">https://doi.org/10.1007/978-3-319-42037-0</a><br/>Format: Electronic Resources<br/>Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environmentent://SD_ILS/0/SD_ILS:2235252024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Sklavos, Nicolas. editor.<br/><a href="https://doi.org/10.1007/978-3-319-44318-8">https://doi.org/10.1007/978-3-319-44318-8</a><br/>Format: Electronic Resources<br/>Model-Implementation Fidelity in Cyber Physical System Designent://SD_ILS/0/SD_ILS:2239332024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Molnos, Anca. editor.<br/><a href="https://doi.org/10.1007/978-3-319-47307-9">https://doi.org/10.1007/978-3-319-47307-9</a><br/>Format: Electronic Resources<br/>Handbook of Hardware/Software Codesignent://SD_ILS/0/SD_ILS:2243402024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Ha, Soonhoi. editor.<br/><a href="https://doi.org/10.1007/978-94-017-7267-9">https://doi.org/10.1007/978-94-017-7267-9</a><br/>Format: Electronic Resources<br/>Automatic Methods for the Refinement of System Models From the Specification to the Implementationent://SD_ILS/0/SD_ILS:2236122024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Seiter, Julia. author.<br/><a href="https://doi.org/10.1007/978-3-319-41480-5">https://doi.org/10.1007/978-3-319-41480-5</a><br/>Format: Electronic Resources<br/>Fundamentals of Computer Architecture and Designent://SD_ILS/0/SD_ILS:2237082024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Bindal, Ahmet. author.<br/><a href="https://doi.org/10.1007/978-3-319-25811-9">https://doi.org/10.1007/978-3-319-25811-9</a><br/>Format: Electronic Resources<br/>Embedded Software Verification and Debuggingent://SD_ILS/0/SD_ILS:2244562024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Lettnin, Djones. editor.<br/><a href="https://doi.org/10.1007/978-1-4614-2266-2">https://doi.org/10.1007/978-1-4614-2266-2</a><br/>Format: Electronic Resources<br/>IP Cores Design from Specifications to Production Modeling, Verification, Optimization, and Protectionent://SD_ILS/0/SD_ILS:167482024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Mohamed, Khaled Salah. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-22035-2">http://dx.doi.org/10.1007/978-3-319-22035-2</a><br/>Format: Electronic Resources<br/>Languages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2015ent://SD_ILS/0/SD_ILS:176652024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Drechsler, Rolf. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-319-31723-6">http://dx.doi.org/10.1007/978-3-319-31723-6</a><br/>Format: Electronic Resources<br/>Memory Controllers for Mixed-Time-Criticality Systems Architectures, Methodologies and Trade-offsent://SD_ILS/0/SD_ILS:177042024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Goossens, Sven. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-32094-6">http://dx.doi.org/10.1007/978-3-319-32094-6</a><br/>Format: Electronic Resources<br/>Reliable Software for Unreliable Hardware A Cross Layer Perspectiveent://SD_ILS/0/SD_ILS:169992024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Rehman, Semeen. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-25772-3">http://dx.doi.org/10.1007/978-3-319-25772-3</a><br/>Format: Electronic Resources<br/>Design for Manufacturability with Advanced Lithographyent://SD_ILS/0/SD_ILS:166402024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Yu, Bei. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-20385-0">http://dx.doi.org/10.1007/978-3-319-20385-0</a><br/>Format: Electronic Resources<br/>Reversible and Quantum Circuits Optimization and Complexity Analysisent://SD_ILS/0/SD_ILS:176912024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Abdessaied, Nabila. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-31937-7">http://dx.doi.org/10.1007/978-3-319-31937-7</a><br/>Format: Electronic Resources<br/>Distributed Embedded Controller Development with Petri Nets Application to Globally-Asynchronous Locally-Synchronous Systemsent://SD_ILS/0/SD_ILS:166612024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Moutinho, Filipe de Carvalho. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-20822-0">http://dx.doi.org/10.1007/978-3-319-20822-0</a><br/>Format: Electronic Resources<br/>Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing From Algorithm to Architectureent://SD_ILS/0/SD_ILS:168922024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Zhang, Chenxin. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-24004-6">http://dx.doi.org/10.1007/978-3-319-24004-6</a><br/>Format: Electronic Resources<br/>Techniques for Building Timing-Predictable Embedded Systemsent://SD_ILS/0/SD_ILS:171342024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Guan, Nan. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-27198-9">http://dx.doi.org/10.1007/978-3-319-27198-9</a><br/>Format: Electronic Resources<br/>SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applicationsent://SD_ILS/0/SD_ILS:175262024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Mehta, Ashok B. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-30539-4">http://dx.doi.org/10.1007/978-3-319-30539-4</a><br/>Format: Electronic Resources<br/>Engineering Applications of FPGAs Chaotic Systems, Artificial Neural Networks, Random Number Generators, and Secure Communication Systemsent://SD_ILS/0/SD_ILS:179202024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Tlelo-Cuautle, Esteban. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-34115-6">http://dx.doi.org/10.1007/978-3-319-34115-6</a><br/>Format: Electronic Resources<br/>FPGAs for Software Programmersent://SD_ILS/0/SD_ILS:170592024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Koch, Dirk. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-319-26408-0">http://dx.doi.org/10.1007/978-3-319-26408-0</a><br/>Format: Electronic Resources<br/>Smart Systems Integration and Simulationent://SD_ILS/0/SD_ILS:171532024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Bombieri, Nicola. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-319-27392-1">http://dx.doi.org/10.1007/978-3-319-27392-1</a><br/>Format: Electronic Resources<br/>More than Moore Technologies for Next Generation Computer Designent://SD_ILS/0/SD_ILS:199402024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Topaloglu, Rasit O. editor.<br/><a href="http://dx.doi.org/10.1007/978-1-4939-2163-8">http://dx.doi.org/10.1007/978-1-4939-2163-8</a><br/>Format: Electronic Resources<br/>Languages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2013ent://SD_ILS/0/SD_ILS:208062024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Louërat, Marie-Minerve. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-319-06317-1">http://dx.doi.org/10.1007/978-3-319-06317-1</a><br/>Format: Electronic Resources<br/>Multiprocessor Scheduling for Real-Time Systemsent://SD_ILS/0/SD_ILS:212212024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Baruah, Sanjoy. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-08696-5">http://dx.doi.org/10.1007/978-3-319-08696-5</a><br/>Format: Electronic Resources<br/>FPGA Based Accelerators for Financial Applicationsent://SD_ILS/0/SD_ILS:223752024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar De Schryver, Christian. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-319-15407-7">http://dx.doi.org/10.1007/978-3-319-15407-7</a><br/>Format: Electronic Resources<br/>Three-Dimensional Design Methodologies for Tree-based FPGA Architectureent://SD_ILS/0/SD_ILS:229052024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Pangracious, Vinod. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-19174-4">http://dx.doi.org/10.1007/978-3-319-19174-4</a><br/>Format: Electronic Resources<br/>Embedded Systems Design for High-Speed Data Acquisition and Controlent://SD_ILS/0/SD_ILS:209002024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Di Paolo Emilio, Maurizio. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-06865-7">http://dx.doi.org/10.1007/978-3-319-06865-7</a><br/>Format: Electronic Resources<br/>Engineering Embedded Systems Physics, Programs, Circuitsent://SD_ILS/0/SD_ILS:215642024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Hintenaus, Peter. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-10680-9">http://dx.doi.org/10.1007/978-3-319-10680-9</a><br/>Format: Electronic Resources<br/>Trusted Computing for Embedded Systemsent://SD_ILS/0/SD_ILS:213332024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Candaele, Bernard. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-319-09420-5">http://dx.doi.org/10.1007/978-3-319-09420-5</a><br/>Format: Electronic Resources<br/>FPGA Design Best Practices for Team-based Reuseent://SD_ILS/0/SD_ILS:227542024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Simpson, Philip Andrew. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-17924-7">http://dx.doi.org/10.1007/978-3-319-17924-7</a><br/>Format: Electronic Resources<br/>Microarchitecture of Network-on-Chip Routers A Designer's Perspectiveent://SD_ILS/0/SD_ILS:196122024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Dimitrakopoulos, Giorgos. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-4301-8">http://dx.doi.org/10.1007/978-1-4614-4301-8</a><br/>Format: Electronic Resources<br/>Analysis and Design of Networks-on-Chip Under High Process Variationent://SD_ILS/0/SD_ILS:234812024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Ezz-Eldin, Rabab. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-25766-2">http://dx.doi.org/10.1007/978-3-319-25766-2</a><br/>Format: Electronic Resources<br/>Wideband CMOS Receiversent://SD_ILS/0/SD_ILS:228742024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Fernandes, Miguel D. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-319-18920-8">http://dx.doi.org/10.1007/978-3-319-18920-8</a><br/>Format: Electronic Resources<br/>Multi-Net Optimization of VLSI Interconnectent://SD_ILS/0/SD_ILS:195862024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Moiseev, Konstantin. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-0821-5">http://dx.doi.org/10.1007/978-1-4614-0821-5</a><br/>Format: Electronic Resources<br/>Low Power Interconnect Designent://SD_ILS/0/SD_ILS:195872024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Saini, Sandeep. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-1323-3">http://dx.doi.org/10.1007/978-1-4614-1323-3</a><br/>Format: Electronic Resources<br/>Arbitrary Modeling of TSVs for 3D Integrated Circuitsent://SD_ILS/0/SD_ILS:210412024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Salah, Khaled. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-07611-9">http://dx.doi.org/10.1007/978-3-319-07611-9</a><br/>Format: Electronic Resources<br/>Dynamic Memory Management for Embedded Systemsent://SD_ILS/0/SD_ILS:215402024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Atienza Alonso, David. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-10572-7">http://dx.doi.org/10.1007/978-3-319-10572-7</a><br/>Format: Electronic Resources<br/>Emerging Memory Technologies Design, Architecture, and Applicationsent://SD_ILS/0/SD_ILS:194602024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Xie, Yuan. editor.<br/><a href="http://dx.doi.org/10.1007/978-1-4419-9551-3">http://dx.doi.org/10.1007/978-1-4419-9551-3</a><br/>Format: Electronic Resources<br/>Programming Heterogeneous MPSoCs Tool Flows to Close the Software Productivity Gapent://SD_ILS/0/SD_ILS:200002024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Castrillón Mazo, Jerónimo. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-00675-8">http://dx.doi.org/10.1007/978-3-319-00675-8</a><br/>Format: Electronic Resources<br/>SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applicationsent://SD_ILS/0/SD_ILS:196502024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Mehta, Ashok B. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-7324-4">http://dx.doi.org/10.1007/978-1-4614-7324-4</a><br/>Format: Electronic Resources<br/>Embedded Systems Development From Functional Models to Implementationsent://SD_ILS/0/SD_ILS:196072024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Sangiovanni-Vincentelli, Alberto. editor.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-3879-3">http://dx.doi.org/10.1007/978-1-4614-3879-3</a><br/>Format: Electronic Resources<br/>Digital VLSI Design with Verilog A Textbook from Silicon Valley Polytechnic Instituteent://SD_ILS/0/SD_ILS:205472024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Williams, John Michael. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-04789-8">http://dx.doi.org/10.1007/978-3-319-04789-8</a><br/>Format: Electronic Resources<br/>Computing with Memory for Energy-Efficient Robust Systemsent://SD_ILS/0/SD_ILS:196722024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Paul, Somnath. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-7798-3">http://dx.doi.org/10.1007/978-1-4614-7798-3</a><br/>Format: Electronic Resources<br/>Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modelingent://SD_ILS/0/SD_ILS:197822024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Mandal, Ayan. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-9405-8">http://dx.doi.org/10.1007/978-1-4614-9405-8</a><br/>Format: Electronic Resources<br/>Designing 2D and 3D Network-on-Chip Architecturesent://SD_ILS/0/SD_ILS:196112024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Tatas, Konstantinos. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-4274-5">http://dx.doi.org/10.1007/978-1-4614-4274-5</a><br/>Format: Electronic Resources<br/>Routing Algorithms in Networks-on-Chipent://SD_ILS/0/SD_ILS:197122024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Palesi, Maurizio. editor.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-8274-1">http://dx.doi.org/10.1007/978-1-4614-8274-1</a><br/>Format: Electronic Resources<br/>Pipelined Multiprocessor System-on-Chip for Multimediaent://SD_ILS/0/SD_ILS:200452024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Javaid, Haris. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-01113-4">http://dx.doi.org/10.1007/978-3-319-01113-4</a><br/>Format: Electronic Resources<br/>Smart Multicore Embedded Systemsent://SD_ILS/0/SD_ILS:197382024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Torquati, Massimo. editor.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-8800-2">http://dx.doi.org/10.1007/978-1-4614-8800-2</a><br/>Format: Electronic Resources<br/>Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012ent://SD_ILS/0/SD_ILS:200802024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Haase, Jan. editor.<br/><a href="http://dx.doi.org/10.1007/978-3-319-01418-0">http://dx.doi.org/10.1007/978-3-319-01418-0</a><br/>Format: Electronic Resources<br/>Embedded Memory Design for Multi-Core and Systems on Chipent://SD_ILS/0/SD_ILS:197402024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Mohammad, Baker. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-8881-1">http://dx.doi.org/10.1007/978-1-4614-8881-1</a><br/>Format: Electronic Resources<br/>Debugging Systems-on-Chip Communication-centric and Abstraction-based Techniquesent://SD_ILS/0/SD_ILS:207942024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Vermeulen, Bart. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-06242-6">http://dx.doi.org/10.1007/978-3-319-06242-6</a><br/>Format: Electronic Resources<br/>Introduction to Embedded Systems Using Microcontrollers and the MSP430ent://SD_ILS/0/SD_ILS:195982024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Jiménez, Manuel. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-3143-5">http://dx.doi.org/10.1007/978-1-4614-3143-5</a><br/>Format: Electronic Resources<br/>Correct-by-Construction Approaches for SoC Designent://SD_ILS/0/SD_ILS:196752024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Sinha, Roopak. author.<br/><a href="http://dx.doi.org/10.1007/978-1-4614-7864-5">http://dx.doi.org/10.1007/978-1-4614-7864-5</a><br/>Format: Electronic Resources<br/>SystemC and SystemC-AMS in Practice SystemC 2.3, 2.2 and SystemC-AMS 1.0ent://SD_ILS/0/SD_ILS:200502024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Banerjee, Amal. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-01147-9">http://dx.doi.org/10.1007/978-3-319-01147-9</a><br/>Format: Electronic Resources<br/>Scalable and Near-Optimal Design Space Exploration for Embedded Systemsent://SD_ILS/0/SD_ILS:205742024-06-20T02:11:01Z2024-06-20T02:11:01ZYazar Kritikakou, Angeliki. author.<br/><a href="http://dx.doi.org/10.1007/978-3-319-04942-7">http://dx.doi.org/10.1007/978-3-319-04942-7</a><br/>Format: Electronic Resources<br/>